The present invention relates to integrated circuits (ICs) and methods of manufacturing integrated circuits. More particularly, the present invention relates to a method of manufacturing integrated circuits having transistors with elevated source and drain regions.
Currently, deep-submicron complementary metal oxide semiconductor (CMOS) is the primary technology for ultra-large scale integrated (ULSI) devices. Over the last two decades, reducing the size of CMOS transistors and increasing transistor density on ICs has been a principal focus of the microelectronics industry. An ultra-large scale integrated circuit can include over 1 million transistors.
The ULSI circuit can include CMOS field effect transistors (FETS) which have semiconductor gates disposed between drain and source regions. The drain and source regions are typically heavily doped with a P-type dopant (boron) or an N-type dopant (phosphorous).
The drain and source regions generally include a thin extension that is disposed partially underneath the gate to enhance the transistor performance. Shallow source and drain extensions help to achieve immunity to short-channel effects which degrade transistor performance for both N-channel and P-channel transistors. Short-channel effects can cause threshold voltage roll-off and drain-induced barrier-lowering. Shallow source and drain extensions and, hence, controlling short-channel effects, are particularly important as transistors become smaller.
Conventional techniques utilize a double implant process to form shallow source and drain extensions. According to the conventional process, the source and drain extensions are formed by providing a transistor gate structure without sidewall spacers on a top surface of a silicon substrate. The silicon substrate is doped on both sides of the gate structure via a conventional doping process, such as, a diffusion process or an ion implantation process. Without the sidewall spacers, the doping process introduces dopants into a thin region just below the top surface of the substrate to form the drain and source extensions as well as to partially form the drain and source regions.
After the drain and source extensions are formed, silicon dioxide spacers, which abut lateral sides of the gate structure, are provided over the source and drain extensions. With the silicon dioxide spacers in place, the substrate is doped a second time to form deep source and drain regions. During formation of the deep source and drain regions, further doping of the source and drain extensions is inhibited due to the blocking capability of the silicon dioxide spacers.
As the size of transistors disposed on ICs decreases, transistors with shallow and ultra-shallow source/drain extensions become more difficult to manufacture. For example, a small transistor may require ultra-shallow source and drain extensions with less than 30 nanometer (nm) junction depth. Forming source and drain extensions with junction depths of less than 30 nm is very difficult using conventional fabrication techniques. Conventional ion implantation techniques have difficulty maintaining shallow source and drain extensions because point defects generated in the bulk semiconductor substrate during ion implantation can cause the dopant to more easily diffuse (transient enhanced diffusion, TED). The diffusion often extends the source and drain extension vertically into the bulk semiconductor substrate. Also, conventional ion implantation and diffusion-doping techniques make transistors on the IC susceptible to short-channel effects, which result in a dopant profile tail distribution that extends deep into the substrate.
The source region and drain regions can be raised by selective silicon (Si) epitaxy to make connections to source and drain contacts less difficult. The raised source and drain region provide additional material for contact silicidation processes. However, the raised source and drain region do not necessarily make conventional doping processing for source and drain junctions less challenging, especially with respect to transistors with small gate lengths. The spacing between the source and drain regions in devices with gate lengths below 70 nm is extremely narrow (e.g., only 25-30 nm).
According to conventional doping techniques, the dopant implanted into the source and drain region must be activated at temperatures of 900-1100.degree. C. for several seconds. The high temperatures, often referred to as high thermal budget, associated with conventional doping techniques can produce significant thermal diffusion which can cause shorts between the source and drain region (between the source/drain extensions). The potential for shorting between the source and drain region increases as gate lengths decrease.
According to conventional processes (e.g., self-aligned CMOS fabrication processes), the polysilicon gate, source and drain regions are implanted (doped) during the same fabrication step. After doping the gate, source and drain regions, the substrate is subject to a heating process which activates the dopant in the gate, source and drain regions. However, electrical activation of dopants in the gate, deep source region and deep drain region requires a temperature, typically greater than 1050 degrees C., which is higher than temperatures required to activate dopants in the source and drain extensions. The higher temperature increases the active dopant concentration in the gate which gives the transistor more drive current due to reduced gate-depletion effect. In addition, the higher temperature reduces silicide-to-junction resistance by increasing active dopant concentration in the deep source and deep drain regions.
As described above, higher temperatures increase the susceptibility of the transistor to short channel effects. To reduce the potential for short channel effects, formation of ultra-shallow source and drain extensions and tight halo profiles require low rapid thermal anneal (RTA) temperatures (e.g., less than 900 degrees C. in crystalline silicon or less than 800 degrees C. in preamorphized silicon). Therefore, optimizing the heating step for the gate, deep source and drain regions as well as for the drain and source extensions is difficult.
Thus, there is a need for an integrated circuit or electronic device that includes transistors not susceptible to shorts caused by dopant thermal diffusion. Further still, there is a need for transistors with elevated source and drain regions manufactured in an optimized annealing process. Even further still, there is a need for source and drain regions having dopants activated in a low thermal budget (low temperature) process.